# Triadic Memory — A Fundamental Algorithm for Cognitive Computing

**URL:** <https://discourse.numenta.org/t/triadic-memory-a-fundamental-algorithm-for-cognitive-computing/9763>\
**Category:** Related Papers\
**Tags:** sparse-distributed-m\
**Created:** [May 27, 2022, 9:35am UTC](https://discourse.numenta.org/t/triadic-memory-a-fundamental-algorithm-for-cognitive-computing/9763 "2022-05-27T09:35:23Z")\
**Posts on this page:** 1\
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**Author:** ![cezar\_t](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.numenta.org/cezar_t/32/4451_2.png) [@cezar\_t](https://discourse.numenta.org/u/cezar_t)\
**Post date:** [July 26, 2022, 3:33pm UTC](https://discourse.numenta.org/t/triadic-memory-a-fundamental-algorithm-for-cognitive-computing/9763/129 "2022-07-26T15:33:16Z")

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> [@POv](#):
>
> The HTM temporal memory (please correct me if I’m wrong) is a component with one SDR input and one SDR output. From an electrical engineering point of view it’s clear that you cannot build interesting circuits from such a component – this requires components with three ports, such as logical gates, transistors, or … triadic memories.

Actually if the input is doubled in size one half can be used as a controlling context for the other half.

In general any subset of input space bits can be regarded (or used) as a “controlling gate” for the reminder input bitspace.

The main limitation being input and output spaces are same size.

Which is no longer the case with brainblocks .  
There is an explicit [context learner](https://discourse.numenta.org/t/releasing-brainblocks-0-7-1-building-ml-applications-with-htm-like-algorithms/9926/10) class that could be a powerful twist on HTM principles.

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