Hi Jacob!
I’m working on a similar thing in parallel. Maybe we should merge forces?
Do you have a repo anywhere with your project?
I’m more familiar with verilog (system verilog) myself, and will be spending the next couple of days putting serious thought time into this, such as what is required from a chip to carry out learning operations.
My main idea is that you won’t be able to keep state for the htm on an FPGA (just doesn’t have enough memory for that, nor should it). But instead looking at the operations that are required for HTM. I’m envisioning more of an HTM co-processor that works in concert with a CPU (across multiple threads). I’ve outlined how it can be done with current traditional hardware.
In my approach, the “Pool” is just a referee keeping track of which minicolumns best match the current input, picking winning minicolumns. It also keeps track of the winning cells from each of those minicolumns, so that the next timestep’s winning cells know who to update. So there are only four pieces of information that need to be worked on or updated by some device: previouswinners, currentwinners, minicolumn connection strength, and cell connections (not their strengthd… only their connections… brain doesn’t remember “strength” of proximal connections, just that they are there).
So my approach, to break it down:
- Find overlap scores for all columns in a pool.
- Pick “currentwinners!”… top 2%, for example.
- Have currentwinners strengthen their connections to input space
- Have currentwinners update the lists of previous previouswinners so that next time previouswinners “win”, they call out to and “vote” for “currentwinners” (potentially putting them into a predictive state).
- Have currentwinners check their own call list and vote for who they think will win the next round.
For example, for checking the overlap score between a minicolumn and an input space:
- register to store column address in RAM (where results will be shipped out to)
- binary comparator(s) to AND the inputspace bit and column mapping bit
- an accumulators to increment when the AND output is HIGH (tracking score)
- a counter in increment each, up to the input space size value (tracking bit index)
For this step, all we care about is finding overlap score across the columns; results in the counter would be stored out to RAM when index counter reaches its determined value, as the next column’s connection map is loaded in.
For cell selection and voting:
hardware setup (FPGA resources):
- Previous winnercells register (memory addresses to their call-list arrays)
- Current winnercells register (to be filled)
- Registers for cell votes (register size matching number of bits required to hold all the vote values)
- Registers for corresponding cells’ memory addresses
Procedure:
- Load up previous winnercells register with previous timestep’s winners (
- Load up columncell registers with votes and votebox addresses
- Check if column was predictive (could be as simple as a bit flag)
- If predictive, find cell with highest vote count, adding its address to call lists of previouswinners
- If not predictive, find cell with lowest vote count, adding its address to the call lists of previous winners
- Store winning cells call list addresses and current array index value to winnercells register
With these two pieces, it should be possible to implement HTM on an FPGA (at least it seems in my mind…).