By Sebastian Billaudelle & @subutai
Please discuss this paper below.
I’m considering doing a follow-up project on this topic. Unfortunately Sebastian is not on this forum, so I’d like to ask @subutai what he believes should come next. According to the paper, the basic modules of spatial pooling and temporal memory have been implemented successfully, but the learning mechanisms are not directly able to be mapped to the hardware.
In this work, was learning implemented in a digital processor outside of the HICANN chip wafers? In any case, the Plasticity Processing Unit (PPU) that was mentioned is elaborated on here.
The first extension that comes to mind, following the sequence in HTM School as well, is topology. Is any part of the sensorimotor integration theory mature enough to offer algorithms ready for hardware implementation?
Is the implementation of the port (eg. the pyNN code) available and any other supporting material?
@Oblynx: i discussed last Friday with Prof Karlheinz Meier, results were good, but there is no further activity on this topic more!
Hi @Oblynx,
It would be great to have someone continue this project. As @thanh-binh.to mentioned, currently there is no activity going on. However much of the work was done in simulations and could be carried on.
Doing learning properly within a two-compartment LIF model is a big piece that could be completed. You mentioned topology, which is another piece that could be tackled. It could help the models scale to larger simulations. In general, implementing HTM in continuous time neuron models is a pretty interesting area. Successful models would help neuroscientists understand HTM better.
The source code is available here (I haven’t looked at it too much, so don’t know if pieces are missing):
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