SDR per bit capacity bottleneck?

Lets have a TM with columns of 3 rows, just for the example.
Lets now follow the states that a single bit can represent.
It would be possible for this bit to accommodate 3 states.
For the following sequences :

A:X1:Y1:B
C:X2:Y2:D
E:X3:Y3:F
G:X4:Y4:H
J:X5:Y5:K

Now this bit will uniquely be able to represent only the first 3 sequences.
after that it has to reuse ‘rows’, which will conflict with previous representation .

m’I missing something ?
How do we handle this situation ?